Compared with other display technologies, LED display has the advantages of self illumination, excellent color reproduction, high refresh rate, power saving, easy maintenance, etc. The two characteristics of high brightness and super large size through splicing are the decisive factors for the rapid growth of led display in the past two decades. In the field of large screen outdoor display, there is no other technology that can compete with LED display technology.

However, in the past, led display has its shortcomings, such as the large spacing between encapsulated lamp beads, resulting in low resolution, which is not suitable for indoor and close viewing. In order to improve the resolution, it is necessary to reduce the spacing between the lamp beads. However, the size of the lamp beads is reduced. Although the resolution of the whole screen can be improved, the cost will also rise rapidly. The high cost affects the large-scale commercial application of small spacing LED displays.

In recent years, thanks to the efforts of chip manufacturers and packaging manufacturers, IC circuit manufacturers and screen manufacturers, the cost of single packaging devices is getting lower and lower, LED packaging devices are getting smaller and smaller, the pixel spacing of display screen is getting smaller and smaller, and the resolution is getting higher and higher, making the advantages of small spacing LED display screen in large indoor screen display more and more obvious.

At present, small pitch LED is mainly used in advertising media, stadiums and gymnasiums, stage background, municipal engineering and other fields, and continues to expand the market in transportation, broadcasting, military and other fields. It is estimated that by 2018, the market size will be close to 10 billion. It can be predicted that in the next few years, small pitch LED displays will continue to expand their market share and occupy the market space of DLP rear projection. According to the prediction of Everbright Securities Research Institute, by 2020, the replacement rate of small spacing LED displays for DLP rear projection will reach 70%~80%.

The author is engaged in the blue and green LED chip manufacturing industry and has been engaged in product development for many years. Next, from the perspective of product design and process technology, we will discuss the demand for blue and green LED chips from the development of small pitch LED displays, as well as the possible solutions on the chip side.

2、 The demand of small pitch LED display screen for LED chip

As the core of LED display screen, LED chip plays a crucial role in the development of small pitch LED. The current achievements and future development of small spacing led display depend on the unremitting efforts of the chip.

On the one hand, the point spacing of indoor display screen gradually decreased from P4 in the early stage to P1.5, P1.0 and P0.8 in development. Correspondingly, the size of lamp beads has been reduced from 3535 and 2121 to 1010. Some manufacturers have developed 0808 and 0606 sizes, and even some manufacturers are developing 0404 sizes.

As we all know, the size reduction of packaged lamp beads inevitably requires the reduction of chip size. At present, the surface area of the common blue-green chips for small pitch displays in the market is about 30 mil 2, and some chip factories are already mass producing 25 mil 2 or even 20 mil 2 chips.

On the other hand, with the decrease of chip surface area and single core brightness, a series of problems affecting display quality have become prominent.

The first is the requirement for gray scale. Different from the outdoor screen, the difficulty of indoor screen demand is not brightness but grayscale. At present, the brightness demand of indoor large spacing screens is about 1500 cd/m2 - 2000 cd/m2. The brightness of small spacing LED displays is generally about 600 cd/m2 - 800 cd/m2, while the optimal brightness for long-term eye-catching displays is about 100 cd/m2 - 300 cd/m2.

At present, one of the difficulties of small pitch LED screen is "low brightness and low gray". That is, the gray level under low brightness is not enough. To achieve "low brightness and high gray", the current package end adopts the black bracket. Due to the weak reflection of the black bracket on the chip, the chip is required to have sufficient brightness.

The second is the display uniformity. Compared with the conventional screen, the smaller the spacing will lead to problems such as afterglow, dark first scan, low brightness and red, and uneven low gray. At present, efforts have been made at the package end and IC control end to solve the problems of afterglow, darkening of the first scan, and reddening of low gray, which have been effectively alleviated. The brightness uniformity problem under low gray is also alleviated by point by point correction technology. However, as one of the root causes of the problem, the chip side needs more efforts. Specifically, the brightness uniformity under low current is better, and the consistency of parasitic capacitance is better.

The third is reliability. The current industry standard is that the allowable value of LED dead light rate is 1/10000, which is obviously not applicable to small pitch LED displays. Due to the large pixel density of the small spacing screen and the close viewing distance, if there is one dead light for 10000 screens, the effect is unacceptable. In the future, the dead light rate needs to be controlled at 1/100000 or even 1/1000000 to meet the demand for long-term use.

In general, the development of small pitch LED requires the chip to be smaller in size, higher in relative brightness, better in brightness consistency under small current, better in parasitic capacitance consistency, and higher in reliability.

3、 On chip solutions

1. Size reduction Chip size reduction

On the surface, it seems that the problem of layout design can be solved by designing smaller layouts as needed. However, can the reduction of chip size go on indefinitely? The answer is no. There are several reasons that restrict the reduction of chip size:

(1) Limitations on packaging processing. In the process of packaging, two factors limit the reduction of chip size. One is the limitation of suction nozzle. The fixed crystal needs to suck the chip, and the size of the short side of the chip must be greater than the inner diameter of the suction nozzle. At present, the inner diameter of cost-effective suction nozzle is about 80um. The second is the limit of welding line. First of all, the wire reel, i.e. the chip electrode, must be large enough, otherwise the reliability of the wire cannot be guaranteed. The minimum electrode diameter reported in the industry is 45um; Secondly, the distance between electrodes must be large enough, otherwise the two welding lines will inevitably interfere with each other.

(2) The limitation of chip processing. There are also two limitations in chip processing. One is the limitation of layout. In addition to the above restrictions on the package end, electrode size and electrode spacing, the distance between the electrode and MESA, the width of the scribed line, and the boundary line spacing of different layers have their limitations. The current characteristics of the chip, SD process capability, and photolithography processing capability determine the specific limits. Generally, the minimum distance from the P electrode to the chip edge is limited to 14 μ M above.

The second is the limitation of the ability of the crack cutting processing. SD scribing+mechanical slicing process has limits, and chip size is too small to be cracked. When the wafer diameter increases from 2 inches to 4 inches, or in the future to 6 inches, the difficulty of slicing will increase, that is, the size of the chip that can be processed will increase accordingly. Take a 4-inch chip for example, if the length of the short side of the chip is less than 90 μ m. If the aspect ratio is greater than 1.5:1, the yield loss will increase significantly.

Based on the above reasons, the author boldly predicts that after the chip size is reduced to 17mil2, the chip design and processing capacity will approach the limit, and there is basically no room for reduction, unless there is a major breakthrough in the chip technology scheme.

2. Brightness improvement

Brightness improvement is an eternal theme on the chip. The chip factory improves the internal quantum effect by optimizing the epitaxial program, and improves the external quantum effect by adjusting the chip structure.

However, on the one hand, the reduction of chip size will inevitably lead to the reduction of luminous area and the decline of chip brightness. On the other hand, the dot spacing of small pitch displays is reduced, and the demand for single chip brightness is reduced. There is a complementary relationship between the two, but there should be a bottom line. At present, in order to reduce the cost, the chip side mainly makes subtraction on the structure, which usually pays the price of brightness reduction. Therefore, how to balance the trade-offs is a problem that the industry should pay attention to.

3. Consistency under low current

The so-called small current is relative to the current used in conventional indoor and outdoor chip trials. As shown in the figure below, the I-V curve of the chip shows that the conventional indoor and outdoor chips work in the linear working area, and the current is large. The small spacing LED chip needs to work in the nonlinear working area near the zero point, and the current is small.

In the nonlinear working area, LED chips are affected by semiconductor switch threshold, and the difference between chips is more obvious. It is easy to see that the discreteness of nonlinear working area is much greater than that of linear working area when analyzing the discreteness of brightness and wavelength of large batches of chips. This is an inherent challenge on the chip.

The solution to this problem is first to optimize the extension direction, mainly to reduce the lower limit of the linear working area; The second is the optimization of chip light distribution, which distinguishes chips with different characteristics.

4. Parasitic capacitance consistency

At present, there is no condition to directly measure the capacitance characteristics of the chip. The relationship between capacitance characteristics and conventional measurement items is not yet clear, so there are people waiting for work to summarize. The direction of chip side optimization is to adjust epitaxy and refine electrical classification, but the cost is very high, so it is not recommended.

5. Reliability

The reliability of chip can be described by the parameters in the process of chip packaging and aging. But in general, the factors that affect the reliability of the chip after it is put on the screen focus on ESD and IR.

ESD refers to anti-static capability. According to IC industry reports, more than 50% of chip failures are related to ESD. To improve the reliability of the chip, the ESD capability must be improved. However, under the condition of the same epitaxial chip and the same chip structure, the smaller chip size will inevitably weaken the ESD capability. This is directly related to current density and chip capacitance characteristics, which is irresistible.

IR refers to reverse leakage, usually measuring the reverse current value of the chip under a fixed reverse voltage. IR reflects the number of internal defects of the chip. The higher the IR value, the more defects in the chip.

To improve ESD capability and IR performance, more optimization must be made in epitaxial structure and chip structure. During chip grading, strict grading standards can effectively eliminate chips with weak ESD capability and IR performance, thus improving the reliability of chips after being put on the screen.

4、 Summary

To sum up, the author analyzed the series of challenges faced by LED chips with the development of small pitch LED displays, and gave improvement plans or directions one by one. It should be said that there is still much room for the optimization of LED chips. How to improve? The unemployed should exert their intelligence and make continuous efforts.

Compared with other display technologies, LED display has the advantages of self illumination, excellent color reproduction, high refresh rate, power saving, easy maintenance, etc. The two characteristics of high brightness and super large size through splicing are the decisive factors for the rapid growth of led display in the past two decades. In the field of large screen outdoor display, there is no other technology that can compete with LED display technology.

However, in the past, led display has its shortcomings, such as the large spacing between encapsulated lamp beads, resulting in low resolution, which is not suitable for indoor and close viewing. In order to improve the resolution, it is necessary to reduce the spacing between the lamp beads. However, the size of the lamp beads is reduced. Although the resolution of the whole screen can be improved, the cost will also rise rapidly. The high cost affects the large-scale commercial application of small spacing LED displays.

In recent years, thanks to the efforts of chip manufacturers and packaging manufacturers, IC circuit manufacturers and screen manufacturers, the cost of single packaging devices is getting lower and lower, LED packaging devices are getting smaller and smaller, the pixel spacing of display screen is getting smaller and smaller, and the resolution is getting higher and higher, making the advantages of small spacing LED display screen in large indoor screen display more and more obvious.

At present, small pitch LED is mainly used in advertising media, stadiums and gymnasiums, stage background, municipal engineering and other fields, and continues to expand the market in transportation, broadcasting, military and other fields. It is estimated that by 2018, the market size will be close to 10 billion. It can be predicted that in the next few years, small pitch LED displays will continue to expand their market share and occupy the market space of DLP rear projection. According to the prediction of Everbright Securities Research Institute, by 2020, the replacement rate of small spacing LED displays for DLP rear projection will reach 70%~80%.

The author is engaged in the blue and green LED chip manufacturing industry and has been engaged in product development for many years. Next, from the perspective of product design and process technology, we will discuss the demand for blue and green LED chips from the development of small pitch LED displays, as well as the possible solutions on the chip side.

2、 The demand of small pitch LED display screen for LED chip

As the core of LED display screen, LED chip plays a crucial role in the development of small pitch LED. The current achievements and future development of small spacing led display depend on the unremitting efforts of the chip.

On the one hand, the point spacing of indoor display screen gradually decreased from P4 in the early stage to P1.5, P1.0 and P0.8 in development. Correspondingly, the size of lamp beads has been reduced from 3535 and 2121 to 1010. Some manufacturers have developed 0808 and 0606 sizes, and even some manufacturers are developing 0404 sizes.

As we all know, the size reduction of packaged lamp beads inevitably requires the reduction of chip size. At present, the surface area of the common blue-green chips for small pitch displays in the market is about 30 mil 2, and some chip factories are already mass producing 25 mil 2 or even 20 mil 2 chips.

On the other hand, with the decrease of chip surface area and single core brightness, a series of problems affecting display quality have become prominent.

The first is the requirement for gray scale. Different from the outdoor screen, the difficulty of indoor screen demand is not brightness but grayscale. At present, the brightness demand of indoor large spacing screens is about 1500 cd/m2 - 2000 cd/m2. The brightness of small spacing LED displays is generally about 600 cd/m2 - 800 cd/m2, while the optimal brightness for long-term eye-catching displays is about 100 cd/m2 - 300 cd/m2.

At present, one of the difficulties of small pitch LED screen is "low brightness and low gray". That is, the gray level under low brightness is not enough. To achieve "low brightness and high gray", the current package end adopts the black bracket. Due to the weak reflection of the black bracket on the chip, the chip is required to have sufficient brightness.

The second is the display uniformity. Compared with the conventional screen, the smaller the spacing will lead to problems such as afterglow, dark first scan, low brightness and red, and uneven low gray. At present, efforts have been made at the package end and IC control end to solve the problems of afterglow, darkening of the first scan, and reddening of low gray, which have been effectively alleviated. The brightness uniformity problem under low gray is also alleviated by point by point correction technology. However, as one of the root causes of the problem, the chip side needs more efforts. Specifically, the brightness uniformity under low current is better, and the consistency of parasitic capacitance is better.

The third is reliability. The current industry standard is that the allowable value of LED dead light rate is 1/10000, which is obviously not applicable to small pitch LED displays. Due to the large pixel density of the small spacing screen and the close viewing distance, if there is one dead light for 10000 screens, the effect is unacceptable. In the future, the dead light rate needs to be controlled at 1/100000 or even 1/1000000 to meet the demand for long-term use.

In general, the development of small pitch LED requires the chip to be smaller in size, higher in relative brightness, better in brightness consistency under small current, better in parasitic capacitance consistency, and higher in reliability.

3、 On chip solutions

1. Size reduction Chip size reduction

On the surface, it seems that the problem of layout design can be solved by designing smaller layouts as needed. However, can the reduction of chip size go on indefinitely? The answer is no. There are several reasons that restrict the reduction of chip size:

(1) Limitations on packaging processing. In the process of packaging, two factors limit the reduction of chip size. One is the limitation of suction nozzle. The fixed crystal needs to suck the chip, and the size of the short side of the chip must be greater than the inner diameter of the suction nozzle. At present, the inner diameter of cost-effective suction nozzle is about 80um. The second is the limit of welding line. First of all, the wire reel, i.e. the chip electrode, must be large enough, otherwise the reliability of the wire cannot be guaranteed. The minimum electrode diameter reported in the industry is 45um; Secondly, the distance between electrodes must be large enough, otherwise the two welding lines will inevitably interfere with each other.

(2) The limitation of chip processing. There are also two limitations in chip processing. One is the limitation of layout. In addition to the above restrictions on the package end, electrode size and electrode spacing, the distance between the electrode and MESA, the width of the scribed line, and the boundary line spacing of different layers have their limitations. The current characteristics of the chip, SD process capability, and photolithography processing capability determine the specific limits. Generally, the minimum distance from the P electrode to the chip edge is limited to 14 μ M above.

The second is the limitation of the ability of the crack cutting processing. SD scribing+mechanical slicing process has limits, and chip size is too small to be cracked. When the wafer diameter increases from 2 inches to 4 inches, or in the future to 6 inches, the difficulty of slicing will increase, that is, the size of the chip that can be processed will increase accordingly. Take a 4-inch chip for example, if the length of the short side of the chip is less than 90 μ m. If the aspect ratio is greater than 1.5:1, the yield loss will increase significantly.

Based on the above reasons, the author boldly predicts that after the chip size is reduced to 17mil2, the chip design and processing capacity will approach the limit, and there is basically no room for reduction, unless there is a major breakthrough in the chip technology scheme.

2. Brightness improvement

Brightness improvement is an eternal theme on the chip. The chip factory improves the internal quantum effect by optimizing the epitaxial program, and improves the external quantum effect by adjusting the chip structure.

However, on the one hand, the reduction of chip size will inevitably lead to the reduction of luminous area and the decline of chip brightness. On the other hand, the dot spacing of small pitch displays is reduced, and the demand for single chip brightness is reduced. There is a complementary relationship between the two, but there should be a bottom line. At present, in order to reduce the cost, the chip side mainly makes subtraction on the structure, which usually pays the price of brightness reduction. Therefore, how to balance the trade-offs is a problem that the industry should pay attention to.

3. Consistency under low current

The so-called small current is relative to the current used in conventional indoor and outdoor chip trials. As shown in the figure below, the I-V curve of the chip shows that the conventional indoor and outdoor chips work in the linear working area, and the current is large. The small spacing LED chip needs to work in the nonlinear working area near the zero point, and the current is small.

In the nonlinear working area, LED chips are affected by semiconductor switch threshold, and the difference between chips is more obvious. It is easy to see that the discreteness of nonlinear working area is much greater than that of linear working area when analyzing the discreteness of brightness and wavelength of large batches of chips. This is an inherent challenge on the chip.

The solution to this problem is first to optimize the extension direction, mainly to reduce the lower limit of the linear working area; The second is the optimization of chip light distribution, which distinguishes chips with different characteristics.

4. Parasitic capacitance consistency

At present, there is no condition to directly measure the capacitance characteristics of the chip. The relationship between capacitance characteristics and conventional measurement items is not yet clear, so there are people waiting for work to summarize. The direction of chip side optimization is to adjust epitaxy and refine electrical classification, but the cost is very high, so it is not recommended.

5. Reliability

The reliability of chip can be described by the parameters in the process of chip packaging and aging. But in general, the factors that affect the reliability of the chip after it is put on the screen focus on ESD and IR.

ESD refers to anti-static capability. According to IC industry reports, more than 50% of chip failures are related to ESD. To improve the reliability of the chip, the ESD capability must be improved. However, under the condition of the same epitaxial chip and the same chip structure, the smaller chip size will inevitably weaken the ESD capability. This is directly related to current density and chip capacitance characteristics, which is irresistible.

IR refers to reverse leakage, usually measuring the reverse current value of the chip under a fixed reverse voltage. IR reflects the number of internal defects of the chip. The higher the IR value, the more defects in the chip.

To improve ESD capability and IR performance, more optimization must be made in epitaxial structure and chip structure. During chip grading, strict grading standards can effectively eliminate chips with weak ESD capability and IR performance, thus improving the reliability of chips after being put on the screen.

4、 Summary

To sum up, the author analyzed the series of challenges faced by LED chips with the development of small pitch LED displays, and gave improvement plans or directions one by one. It should be said that there is still much room for the optimization of LED chips. How to improve? The unemployed should exert their intelligence and make continuous efforts.